Block schematic for yampp-2. Click image for larger version.
However, their player had tons of unnecessary HW (just kidding ;-)
Anyway, I rationalized the HW a bit and left out a few of the chips they had on their player. The leftout
circuits are then compensated by software.
The 8515, 74HC573 and 65256 SRAM, forms a "standard" block, common for Atmel and 8051 circuits.
The decoder and D/A converter is controlled via an 400 kbps I2C bus interface, and the MPEG data is streamed from
the CPU to the decoder through the 2 MHz SPI interface.
An I2S bus carries data from the decoder to the D/A converter.
The LCD display is hooked onto the databus. R/W and RS is controlled by 2 address lines and the enable line is
controlled by an I/O pin.
What's unique here is the way the IDE interface is connected, without the use of buffers or latches.
Here's how it's controlled (this also to some extent applies to the LCD) :
The external RAM interface on the Atmel CPU can be enabled/disabled in a register. When the interface is enabled,
the RD and WR signals as well as the data and address bus works "normally". When the interface is disabled, the
port pins (PORTA [D0-8], PORTC [A8-15], RD and WR), will hold their assigned state from the port registers. Also,
the ALE pin will be disabled.
This, together with the way the ALE pin handles address latching, means that we can latch an address on A0-A7 by
doing a dummy read at the specified address. We can then disable the RAM interface, and the address will still be
held at A0-A7. But PORTA and PORTC is now available for I/O, and we now use them as a 16-bit interface to the IDE
interface.
more to come